@TechReport{SilvaAlMoRiOlCaLu:2015:EsCaSo,
author = "Silva, Francisco de Assis Tavares Ferreira da and Almeida Filho,
Magno Prud{\^e}ncio de and Moreira, Nicolas de Ara{\'u}jo and
Rios, Clauson Sales do Nascimento and Oliveira, Paulo Daving Lima
de and Camur{\c{c}}a, Paulo Jarbas and Lucena, Ant{\^o}nio
Macilio Pereira de",
title = "Modelagem matem{\'a}tica em microeletr{\^o}nica
reconfigur{\'a}vel: estudo de caso sobre moduladores BPSK",
institution = "Instituto Nacional de Pesquisas Espaciais",
year = "2015",
type = "RPQ",
number = "INPE-17549-RPE/911",
address = "S{\~a}o Jos{\'e} dos Campos",
keywords = "FPGA, microeletr{\^o}nica reconfigur{\'a}vel, subsistemas de
comunica{\c{c}}{\~a}o, aplica{\c{c}}{\~o}es espaciais,
moduladores BPSK, FPGA, reconfigurable microelectronic,
communication subsystems, spatial applications, BPSK modulators.",
abstract = "Este relat{\'o}rio apresenta uma metodologia para modelagem
matem{\'a}tica de subsistemas eletr{\^o}nicos a serem simulados,
em ambiente computacional, e emulados, em circuitos integrados
baseados em microeletr{\^o}nica reconfigur{\'a}vel tipo FPGA
(Field Programmable Gate Array) gen{\'e}rico. O processo de
desenvolvimento {\'e} iniciado a partir das express{\~o}es
matem{\'a}ticas, as quais definem o modelo de
simula{\c{c}}{\~a}o computacional. Em seguida, {\'e} utilizado
um compilador o qual converte, automaticamente, o modelo
matem{\'a}tico, simulado, em c{\'o}digos tipo HDL (Hardware
Description Language), os quais podem ser aproveitados por FPGAs
gen{\'e}ricos. Para exemplificar o processo de desenvolvimento,
foram considerados v{\'a}rios aplicativos necess{\'a}rios
{\`a}s etapas de representa{\c{c}}{\~a}o e
simula{\c{c}}{\~a}o de modelos matem{\'a}ticos, considerando um
estudo de caso sobre moduladores BPSK (Binary Phase Shift Keying),
e as respectivas defini{\c{c}}{\~o}es para emula{\c{c}}{\~a}o
em hardware. ABSTRACT: This report presents a mathematical
modeling methodology applied to electronic subsystems development
to be simulated in a computer environment and emulated in
integrated circuits based on reconfigurable microelectronics as
generic FPGA (Field Programmable Gate Array). The development
process starts from the mathematical expressions, which define the
computer simulation model. In a second stage this simulated model
is feed to a compiler which automatically converts the
mathematical model simulated to HDL codes (Hardware Description
Language), which can be applied to generic FPGAs. To illustrate
the development process, the necessary software is presented as
well the steps for the representation, simulation and hardware
emulation of the mathematical models. For that, a case study on
BPSK modulators (Binary Phase Shift Keying) is considered to be
applied on reconfigurable modulation experiments.",
affiliation = "{Instituto Nacional de Pesquisas Espaciais (INPE)} and {} and {}
and {} and {} and {} and {Instituto Nacional de Pesquisas
Espaciais (INPE)}",
copyholder = "SID/SCD",
language = "pt",
pages = "66",
ibi = "8JMKD3MGP3W34P/3JJ6M6E",
url = "http://urlib.net/ibi/8JMKD3MGP3W34P/3JJ6M6E",
targetfile = "publicacao.pdf",
urlaccessdate = "28 abr. 2024"
}